Information storage element, manufacturing method thereof, and memory array

ABSTRACT

An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity ( 6 ), and a floating gate layer ( 5 ) having two stable deflection states in the cavity ( 6 ), the state stabilized by deflecting toward the channel side of transistor, and the state stabilized by deflecting toward the gate ( 7 ) side, writing and reading of information can be made by changing the stable deflection state of the floating gate layer ( 5 ) by Coulomb interactive force between the electrons (or positive holes  8 ) accumulated in the floating gate layer ( 5 ) and external electric field, and by reading the channel current change based on the state of the floating gate layer ( 5 ).

TECHNICAL FIELD

The present invention relates to a flash EEPROM (electrically erasableand programmable read only memory) type non-volatile memory devicebelonging to one of semiconductor memory devices, a method ofmanufacturing the same, and a memory array of using it, especially to aninformation memory device characterized in the part of reading andwriting of information, which are done by mechanical state change of afloating gate layer.

BACKGROUND ART

Heretofore, a flash memory has been known as one of non-volatile memorydevices. The memory cell of the flash memory has a structure comprisinga floating gate formed on a substrate via a tunnel oxide film, and acontrol gate formed via a gate insulation film, which are laminated witheach other. In an operation of the memory cell, upon writing, electrons(or positive holes) are injected from a drain of the memory cell to thefloating gate by using a voltage difference between the control gate andthe drain.

On the other hand, upon erasing, electrons (or positive holes) in thefloating gate are released into the drain by using a controlled voltagedifference between the control gate and the drain. Assuming a substrateas P type, and a source and a drain as n type, a channel of the memorycell becomes off state in case that the floating gate has electrons, andon state in case that it has no electron, so that it operates as anon-volatile memory.

As conventional flash memories, FLOTOX (floating-gate tunnel oxide)types and MNOS (metal nitride oxide semiconductor) type are known.FLOTOX type has a structure comprising a tunnel oxide film (first gateinsulation film), a floating gate, an interlayer insulation film (secondgate insulation film), and a control gate laminated on a channel formedon a surface of a semiconductor substrate, and accumulates electriccharges in the floating gate or releases them into the channel byapplying controlled voltage difference either to generate an accumulatedstate or an erased state, and carry out writing and reading of 1 bitinformation by using the accumulated state and the erased state. MNOStype has a structure comprising two layers of insulation film made ofoxide film (silicon oxide film) and nitride film, and accumulateselectric charges into the trap of interface of two films thereof.

Also in contrast to those electrical memory, there are a mechanicalnon-volatile memory, for example, using a mechanical pendulum andothers, which is seemed to be technologically closest in the field ofrealizing mechanical memory to the present invention (for example, seePhysical Review Letters, Vol. 87, p. 096101-1, 2001.).

General description of Electrical flash memories are described invarious journals (for example, see Electronic Materials, Kogyo Chosakai,April, 1993, p. 32, or LSI Handbook, Ohmsha, edited by The Institute ofElectronics, Information, and Communication Engineers, Nov. 30, 1984, p.485.). However, in the above-mentioned electrical flash memories, thematerial existing between the floating gate and the drain, through whichthe electric current of writing flows, is deteriorated by the current,and the repetition of the writing causes the formation of leakagecurrent path between the floating gate and the drain, thereby arestriction for the times capable of writing arises. That is, since theelectrons or positive holes accumulated in the floating gate flow outthrough the leakage current path formed by the repetition, there is aproblem to be solved that the repetition of writing causes the memorynot to operate as a non-volatile memory.

The object of the present invention is to provide an information memorydevice capable of writing an information by mechanical operation of afloating gate layer, a method of manufacturing the same, and a memoryarray of using it, by which the above problem can be solved.

DISCLOSURE OF THE INVENTION

In order to achieve the object described above, the information memorydevice according to the present invention, in a semiconductor transistorhaving a semiconductor substrate, a source, a drain, a gate, and a gateinsulation film, characterized in that, the gate insulation film has acavity, and a floating gate layer in said cavity having two stabledeflection states, the stable states deflecting toward the channel sideand toward the gate side of said transistor, wherein an information ismemorized by said two stable deflection states of the floating gatelayer.

The information memory device of this makeup operates as describedbelow. By applying an initializing voltage between the gate and thedrain, electric charges are injected into the floating gate layer, aswell as it is initialized to the one state of two stable deflectionstates of the floating gate layer. Next, in order to change the stabledeflection state without changing the amount of injected charges of thefloating gate, a writing voltage being lower than the initializingvoltage is applied. By changing or not changing the stable deflectionstate of the floating gate by means of selecting the sign of writingvoltage, it is possible to write an information in it. If the stabledeflection state of floating gate is the deflection state deflectingtoward the channel side, then influence of electric field of the chargesto the channel is large, and if it is the state deflecting toward thegate side, then influence of electric field of the charges to thechannel is small, so that a written information can be read out bydetecting a magnitude of the current between source and drain.

For example, if the floating gate is firstly stabilized at the statedeflecting toward the channel side, and the initializing voltage beingpositive at the drain and negative at the gate is applied, then holesare injected into the floating gate, and then the floating gate isstabilized as being deflected toward the gate side by the Coulombinteractive force between the injected hole charges and the electricfield directing from the drain toward the gate. Next, if the writingvoltage being negative at the drain and positive at the gate is applied,since the amount of injected holes of floating gate does not change, thefloating gate is stabilized as being deflected toward the gate side bythe Coulomb interactive force between the injected hole charges and theelectric field directing from the gate toward the drain. Since thefloating gate having hole charges approaches to the channel, aconductivity of the channel changes, then a magnitude of the currentbetween the source and drain changes.

The gate insulation film of the information memory device of the presentinvention is preferably made of silicon oxide. The floating gate layeris preferably a silicon oxide layer containing crystalline silicongrains. According to this make-up, since the electron affinity andionization energy of crystalline silicon are large, the injected chargesin the floating gate layer are well stored, and are not changed by thewriting voltage.

Also, the floating gate layer may have the structure to sandwich apolycrystal silicon thin film layer with silicon oxide layers. Also, theeach thickness of the two silicon oxide layers sandwiching a polycrystalsilicon thin film layer may be different each other. According to thismake-up, the elastic modulus of the floating gate can be varied in theevery deflective direction, so that, for example, the writing speed canbe made higher. The floating gate layer instead of the above mentionedis preferably a laminated structure of a silicon oxide layer and siliconnitride layer. According to this make-up, since the electric charges areheld at defect states of the interface between the silicon oxide layerand the silicon nitride layer, the injected charges of the floating gateare well stored, and are not changed by the writing voltage.

By the information memory device of above-mentioned make-up, sincewriting is done by the mechanical operation of the floating gate, suchthe deterioration of conventional flash memories can not occur, thatmaterials constituting the current path between the floating gate andthe drain, through which the current of writing flows, is deterioratedby the current thereof.

The method of manufacturing the information memory device according tothe present invention is explained next. The method of manufacturing theinformation memory device according to the present invention, in asemiconductor transistor having a semiconductor substrate, a source, adrain, a gate, and a gate insulation film, for making a gate insulationfilm which has a cavity and a floating gate layer in said cavity havingtwo stable deflection states, the stable states deflecting toward thechannel side and toward the gate side of transistor, characterized inthat it comprises the steps of: forming a first silicon oxide layer on asemiconductor substrate by high temperature process; forming a cavingregion for the cavity at the region corresponding to a channel oftransistor by etching said first silicon oxide layer; leaving a siliconnitride layer in said caving region by forming a first silicon nitridelayer on said surface and etching said silicon nitride layer; forming afloating gate layer by low temperature process the temperature of whichis lower than the temperature of said high temperature process; leavinga silicon nitride layer on the region corresponding to said cavityregion by forming a second silicon nitride layer on said surface andetching said second silicon nitride layer; forming a second siliconoxide layer on said surface by said high temperature process and etchinga multi layer structure comprising said second silicon oxide layer, saidfloating gate layer, and said first silicon oxide layer into a shape ofa gate insulation film; forming said cavity by removing said first andsecond silicon nitride layer from said structure etched into the shapeof gate insulation film; and deflecting said floating gate by annealingsaid structure.

In the above-mentioned method, the process in which to form the firstsilicon oxide layer by high temperature process is preferably a thermaloxidation method at 1000° C. or higher, or a high temperature CVD methodat 900° C. or higher. The process in which to form the first and thesecond silicon nitride layers by low temperature process is preferablyby a room temperature plasma CVD method. The process in which to form afloating gate layer at temperature lower than the high temperatureprocess is capable by the CVD method at 700° C. or lower. In thisprocess, the floating gate layer having fine silicon crystal particlesburied in the oxide film is preferably formed by a flow rate control offeedstock gas, and a temperature control of feedstock gas, and/or atemperature control of reactor of the CVD. Also, the other formingmethod of the floating gate layer is characterized in that, it comprisesforming a first silicon oxide layer by CVD method, forming a layerhaving fine silicon crystal particles buried in a oxide film on thefirst silicon oxide layer by a flow rate control of feedstock gas, and atemperature control of feedstock gas, and/or a temperature control ofreactor of the CVD, forming a second silicon oxide layer on said layerby the CVD, wherein each thickness of said first and said second siliconoxide layers are differed with each other. The forming process of thefloating gate layer is also preferably of forming a silicon oxide layerby the CVD, and forming a silicon nitride layer on said silicon oxidelayer by the CVD.

The process to form the cavity by removing the first and second siliconnitride layer from the structure etched into the shape of gateinsulation film may be of etching them from the exposed side surfaces ofsilicon nitride layer of the structure with hydrofluoric acid, and theprocess to anneal the structure and to deflect the floating gate may beof annealing at 300° C. or lower.

According to the above method of manufacturing, the gate insulation filmthat has a cavity, and has a floating gate layer in the cavity havingtwo stable deflection states, the stable states deflecting toward thechannel side and toward the gate side of a transistor can be formed.This formation mechanism is assumed as below. That is, before theannealing, the first and the second silicon oxide layers constitutingthe insulation film have a structure stable at the high processtemperature of the high temperature forming process, namely, thestructure expanded from the stable structure at the annealingtemperature having built-in stress in the structure. And also similarly,before the annealing, the silicon oxide layer constituting a floatinggate has the structure stable at the process temperature of the formingprocess, namely, the structure expanded from the stable structure at theannealing temperature having built-in stress in the structure, but sincethe process temperature for the forming is lower than that of the firstand the second silicon oxide layers, the extent of expansion of thestructure is smaller than that of the first and the second silicon oxidelayers.

Upon annealing the structure comprising the first and the second siliconoxide layers and the silicon oxide layer which constitutes the floatinggate, the built-in stresses of those layers are released and thestructures of those layers shrink to be changed to the structure stableat the annealing temperature, then, since the extent of expansion of thefirst and the second silicon oxide layers has been larger than that ofthe silicon oxide layer constituting the floating gate, the first andthe second silicon oxide layers shrink more greatly. Accordingly it isassumed that, since the floating gate must become longer than the firstand the second silicon oxide layers, the floating gate must be deflectedinside the cavity.

And another assumption may be possible as follows. Upon generating thethermal expansion of floating gate layer by the annealing, since thethermal expansion coefficient of silicon oxide is positive, the floatinggate layer expands sufficiently as a volume relaxation by the thermaltreating and the influence of the space of cavity. And since theexpansion in the direction of film thickness is small enough, thefloating gate layer may extend effectively in the direction of channellength. In this case, since the volume of the gate insulation filmholding the floating gate layer and the substrate holding the gateinsulation film are relatively or sufficiently large, the expansion ofthose are negligible compared to the expansion of the floating gatelayer, and therefore the double stable states of the floating gate layerwhich are advantageous in elastic energy may be generated.

Further, a memory array according to the present invention ischaracterized in that, it uses the information memory device describedabove as a memory cell. In the memory array of such makeup, sinceinformation can be written and read by mechanical operation of thefloating gate, the device is not deteriorated by leak current, and is ofhigh speed and high reliability memory.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will better be understood from the followingdetailed description and the drawings attached hereto showing certainillustrative forms of embodiment of the present invention. In thisconnection, it should be noted that such forms of embodiment illustratedin the accompanying drawings hereof are intended in no way to specify orlimit the present invention but to facilitate an explanation and anunderstanding thereof.

FIG. 1 is a cross-sectional view of the information memory device inaccordance with the first embodiment of the present invention, and (a)shows initialization, (b) off-state, and (c) on-state.

FIG. 2 is a graph for calculation of operating characteristics of theinformation memory device of the present invention.

FIG. 3 is a view illustrating physical parameter for calculation ofoperating speed of the information memory device of the presentinvention.

FIG. 4 is a view illustrating operating speed obtained by calculationand device parameter of the information memory device of the presentinvention.

FIG. 5 is a graph illustrating the gate voltage dependency of draincurrent of the information memory device of the present invention.

FIG. 6 is a graph illustrating the drain voltage dependency of draincurrent in on/off states of the information memory device of the presentinvention.

FIG. 7 is a cross-sectional structural view of the floating gate layerof the present invention, and (a) is the structural view of the floatinggate in accordance with the first embodiment, (b) is the structural viewof the floating gate in accordance with the second embodiment, and (c)is the structural view of the floating gate in accordance with the thirdembodiment.

FIG. 8 is a outline diagram illustrating the method of manufacturing theinformation memory device of the present invention.

FIG. 9 is a view illustrating the memory array using the informationmemory device of the present invention.

FIG. 10 is a block diagram of an information processing apparatus usingthe memory array of the present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

Hereinafter, the appropriate embodiments of the present invention willbe described in detail with reference to the drawing figures using samemarks and symbols for practically identical or corresponding parts. Inthe present embodiment, although accumulated carriers are assumed to bepositive holes, entirely same description is possible even for the casein which accumulated carriers are electrons, by exchanging on and offstates. Also in the present embodiment, although the floating gate layeris described as fixed at its both ends likely so-called supported beam,same description is possible even for the case in which the floatinggate layer is fixed at its single end likely so-called cantilever.

First of all, the first embodiment of an information memory device ofthe present invention is explained.

FIG. 1 is a cross-sectional view of an information memory device inaccordance with the first embodiment of the present invention. In orderto explain the principle of operation, initializing state 1 (a),off-state (b), and on-state (c) are respectively indicated.

The information memory device of the present invention has a source, adrain, and a gate on a semiconductor substrate, and the gate insulationfilm of gate has a floating gate therein, and the floating gate is heldin a space of the gate insulation film. For more definitely, referringto FIG. 1(a), n-type source 2 and drain 3 are formed on p-type siliconsubstrate 1, and on the surface, gate insulation film 4 made of siliconoxide (SiO₂) is formed, and floating gate layer 5 are formed nearby themiddle part of thicness of gate insulation film 4. Floating gate layer 5is made of silicon oxide containing fine silicon crystal particles(diameter 10 to 100 nm), and the fine silicon crystal particles canaccumulate carriers such as electrons or positive holes. In the presentembodiment, although the silicon oxide containing fine silicon crystalparticles is described for an example, a laminated structure which canaccumulate carriers as will be described in the later embodiments can beused.

The circumference of Floating gate layer 5 (excluding the fixed portion)is cavity 6 (filled with air or nitrogen gas) as indicated in the figureas upper-space and lower-space of the Floating gate layer, which is aspace made between Floating gate layer 5 and gate insulation film 4. Thelength of floating gate layer 5 along the surface, directing toward achannel length of the transistor, is made a little longer than thechannel length (0.1 to 1 μm). By this makeup, double stable states arepossible, wherein the elastic energy of floating gate layer becomes morefavorable by the floating gate layer deflecting a little toward up ordown.

For example, if downward force is applied to floating gate layer 5deflecting in cavity 6 toward gate 7 side, that is, deflecting upwardconvexity as shown in the figure, and when the force exceeds a certainvalue, floating gate layer 5 changes to be deflecting in cavity 6 towardthe channel side, that is, deflecting downward concavely as shown in thefigure. The change, from the deflecting downward concavely to thedeflecting upward convexly is the reverse thereof. The method of formingthe floating gate layer being long in the direction of channel lengthwhich is the basis for the mechanical state changing will be describedlater. On the surface of gate insulation film 4 having the featurementioned above, gate electrode 7 made of a metal (or polysilicon) isformed to constitute a device.

Next, the explanation of reading and writing of information of theinformation memory device of the present invention are given. FIG. 1(a)shows the state after initializing which is carried out by only onceafter forming the device. Assuming Vs as source voltage, Vd as drainvoltage, Vg as gate voltage, and Vs=0V, sufficiently high voltagedifference (initializing voltage) between Vg and Vd as Vg<<Vd isapplied. Accordingly, positive holes 8 are accumulated in floating gatelayer 5 by a tunneling current passed through gate insulation film 4from substrate 1. The accumulated state by positive holes are maintainedas far as a voltage which is sufficiently lower than the initializingvoltage between Vg and Vd is applied thereafter.

In order to realize off-state (FIG. 1(b)), a voltage difference betweenVg and Vd (off voltage: Vg<Vd) is applied, which is lower than theinitializing voltage and sufficiently large to change floating gatelayer 5 from concavity to convexity. Thereby, floating gate layer 5becomes convexity state, the average distance between the positive holes8 accumulated in floating gate layer 5 and the channel is made longer,and the electrostatic field applied to the channel from positive holes 8is reduced. Due to the reduction of electric field, p-type channelbecomes in off-state.

On the other hand, on state is realized by applying a voltage differencebetween Vg and Vd (on voltage: Vg>Vd) whose direction is reverse to theoff voltage, whereby floating gate layer 5 becomes to the concavitystate. By the state, floating gate layer 5 approaches to the channelwith magnitude of displacement 9, the electric field applied to thechannel by positive holes 8 increases to make the channel to be in onstate, the current Id arising from voltage difference between Vs and Vdflows, and it becomes possible to function as a memory by reading thecurrent Id.

Next, the operating speed of information memory of the present inventionis explained, referring to FIG. 2. The bold solid line of FIG. 2(a) isthe floating gate layer of the present invention representing as onedimensional model. In case that the film thickness of floating gatelayer is sufficiently thin, and the change of thickness along depth ofthe figure (the channel width direction) is negligible, it can betreated by one-dimensional model. The abscissa x shows the channellength direction, and the ordinate z shows the height in verticaldirection from the substrate. Assuming L₀ as channel length, and L astotal length of the floating gate layer, the floating gate layer isshown by the curve in FIG. 2(a) (an example of convexity state). Here,in case that L and L₀ are nearly equal, the distance Δz between thefloating gate layer and x axis is approximately expressed by Equation(1). $\begin{matrix}{{\Delta\quad z} = {{\frac{1}{2}\sqrt{L^{2} - L_{0}^{2}}} = {\frac{1}{2}\sqrt{\left( {L_{0} + {\kappa\quad L_{0}T}} \right)^{2} - L_{0}^{2}}}}} & (1)\end{matrix}$where T is a temperature, κ is the linear expansion coefficient of thefloating gate layer, and κ=(1/L₀)(d/L₀/dT). As mentioned later, thetemperature T is adapted with the temperature of thermal treatment ofmanufacturing process for forming the device.

The mechanical potential energy of the floating gate layer in theconvexity state is shown as in FIG. 2(b). At z=±Δz, there exist thestable states which have lowest elastic energy, and displacing fromthere increases the potential energy because of the energy loss forcausing strains. Precisely speaking, nearby z=0 and ±Δz, it is theharmonic oscillatory potential (shown by dotted line in FIG. 2(b)), butfor simplicity, it is approximated by linear potential.

Consideration below makes it possible to estimate the potential height.By applying a force F to the floating gate layer in the direction fordecreasing Δz, the length of the floating gate layer is reduced by thelength ΔL. Here the next Equation (2) is realized. $\begin{matrix}{\frac{\Delta\quad L}{L_{0}} = {\frac{\kappa\quad L_{0}T}{L_{0}} = {\frac{F}{S}\alpha}}} & (2)\end{matrix}$where α is the coefficient of compressibility per unit area of thefloating gate layer, S is the surface area of the floating gate layer(channel length×Channel width).

The potential energy height ψ equals to the product (work) of thedistance Δz where the floating gate layer moved till becoming straight(L=L₀) and the force F applied during it. Therefore, Equation (3) asshown below is realized.ψ=F·Δz   (3).

While the floating gate layer is pushed by force F, elastic force foperates. Since f corresponds to the slope of potential ψ, it isexpressed as Equation (4) as shown below. $\begin{matrix}{f = {\frac{\psi}{\Delta\quad z} = {{\frac{S}{\alpha}\frac{\Delta\quad L}{L_{0}}} = {\frac{S\quad\kappa\quad T}{\alpha}.}}}} & (4)\end{matrix}$The force f operates as reaction force to F while z has a value betweenz=+Δz and z=0, and as additional force to F while z has a value betweenz=0 and z=−Δz. In order to change the floating gate layer from convexityto concavity, electric field is applied to the accumulated charge Q inthe floating gate layer by applying a voltage Vg to the gate electrode.Assuming the distance between the gate electrode and the floating gatelayer as d, the motion equation of the floating gate layer in this caseis expressed as Equations (5) and (6) shown below. $\begin{matrix}{{\frac{QVg}{d} - f} = {m\frac{\partial^{2}z}{\partial t^{2}}\left( {z = {{- \Delta}\quad z\quad{to}\quad 0}} \right)}} & (5) \\{{\frac{QVg}{d} + f} = {m\frac{\partial^{2}z}{\partial t^{2}}\left( {z = {{0\quad{to}}\quad + {\Delta\quad z}}} \right)}} & (6)\end{matrix}$wherein m is the total mass of the floating gate layer (excluding thesupported part). By solving those motion equation, the time t_(rw)required for the floating gate layer to move from +Δz to −Δz is obtainedas Equation (7). $\begin{matrix}{t_{RW} = {\sqrt{\frac{2m\quad\Delta\quad z}{\left( \frac{QVg}{d} \right) - \left( \frac{S\quad\kappa\quad T}{\alpha} \right)}} + \sqrt{\frac{2m\quad\Delta\quad z}{\left( \frac{QVg}{d} \right) + \left( \frac{S\quad\kappa\quad T}{\alpha} \right)}}}} & (7)\end{matrix}$

For a case that silicon oxide is considered as the material for thefloating gate layer, physical parameters are as shown in FIG. 3. Byusing those physical parameters, the device parameters are calculatedfor two typical cases that the channel length is 1 μm and 0.1 μm, andthe results are shown in FIG. 4.

Sufficiently high operating speed can be obtained compared with flashmemories of conventional electric memory type, as indicated, theoperating speed is 2.1 GHz for channel length 1 μm and 21 GHz for 0.1μm. Therefore, the information memory device of the present invention,which is a mechanical flash memory, can realize high operating speedwithout the problem of material deterioration by charging anddischarging of electrons.

FIGS. 5 and 6 are graphs showing approximate transportationcharacteristics of the information memory device of the presentinvention. FIG. 5 is a graph illustrating the re-writing process ofinformation by gate voltage Vg. First of all, the floating gate layer isassumed to be in convexity, and accumulated with positive holes. Suchparameters as device size and others are defined as the same of astructural example 1 of FIG. 5. By applying gate voltage Vg from minusside to plus side, the floating gate layer changes from convexity toconcavity at the critical point (about 6V) where the electric fieldapplied to the floating gate layer overcomes the elastic force. Thereby,the channel in off state changes to on state, and drain current Idflows.

Next, by applying Vg from plus to minus side, the floating gate layerchanges from concavity to convexity at the reversal critical point(about −6V), and the channel becomes off. Since the current change ofthis process is a hysteresis curve as shown in FIG. 5, it can operate asa memory with switching voltage Vg about ±20V.

FIG. 6 shows the drain voltage Vd dependency of drain current in on/offstates, respectively. Since the channel is not formed in the case of offstate, the current Id hardly flows even if applying voltage Vd (leakcurrent is about 1×10⁻¹⁵ A), but in the case of on state, since thechannel is fully open, large Id flows. Therefore, by measuring thecurrent, the memorized information can be read out.

The detail of the floating gate layer structure of the present inventionis explained next. The floating gate layer having the longer lengthdirecting toward the channel, which is the basis of mechanical statechange, is formed self-organizingly by using thermal expansion of theconventionally used material such as silicon oxide. The cross-sectionalviews of the structure are shown in FIGS. 7(a) to (c).

FIG. 7(a) is the floating gate layer in accordance with the firstembodiment. The floating gate layer 5 of the first embodiment has thestructure in which silicon crystal particles 10 of about 30 to 50 nmdiameter are buried in silicon oxide 51. The silicon crystal particles10 can be relatively easily formed by flow rate control of the feed gasin chemical vapor deposition method (CVD method), or by temperaturecontrol of the feed gas or reactors, owing to the recent development offilm-making technology. The diameter of the silicon crystal particles 10is preferably 1 to 50 nm. The CVD can be carried out at substratetemperature of 700° C. or lower.

The silicon crystal particles covered by silicon oxide is formed byforming spherical silicon particles and oxidizing the surface of them inthe reactive raw material gas, and then depositing them on a substrate,or by depositing the spherical silicon particles on a substrate withouttheir surface oxidizing and then oxidizing their surfaces by followingthermal treatment. The floating gate layer has film thickness t_(oX) of0.1 to 100 nm, length L of 0.1 to 1 μm, and width of 0.1 to 1 μm, whichare corresponding to the channel length and the channel width. The sizeof floating gate layer is the same in other embodiments.

In the structure thereof, since the silicon crystal which is asemiconductor is isolated in the silicon oxide which is an insulator,electrons (or positive holes 8) transmitted through the silicon oxide bymeans of a tunneling current are accumulated in the crystal silicon. Sofar as a voltage which is lager than that of generating the tunnelingcurrent is not applied, the accumulated electrons (or positive holes 8)are accumulated semi-permanently in the crystal silicon, therefore thisstructure is optimal for the floating gate layer of the presentinvention.

FIG. 7(b) shows a cross-sectional structure of the floating gate layerin accordance with the second embodiment. The floating gate layer 5 ofthe second embodiment has a structure in which a polysilicon thin filmlayer 11 is inserted between two silicon oxide 51. The preferablethickness t_(si) of the polysilicon thin film layer 11 depends on thatof the floating gate layer, but is 1 to 50 nm preferable, which is aboutthe same to the diameter of silicon crystal particles of the firstembodiment. In FIG. 7(b), d indicates the film thickness of siliconoxide on the upper side of the polysilicon thin film layer 11, and isformed in different thickness from the thickness of silicon oxide on thebottom side. In this case, anisotropy of the deflection elastic energywith respect to the deflection direction can be attained by the heightshifting of the semiconductor thin film from the center of filmthickness of the silicon oxide. Thereby, since the elastic constant ofthe floating gate layer with respect to the deflection direction can bechanged, operating speed such as re-writing speed of a memory device andothers can be controlled.

FIG. 7(c) is a cross-sectional structure of the floating gate layer inaccordance with the third embodiment. This has the structure oflamination with two kinds of insulators, silicon oxide film 51 andsilicon nitride film 12. With such a structure, since the process ofmanufacturing is simplified compared with other cases, the cost can bereduced. In this case, the defect 13 on the interface of the twoinsulation layers accumulates electrons (or positive holes). Here, alsoin this third embodiment as in the second, the anisotropy of elasticenergy can be attained by shifting the interface position of insulationlayers upward or downward.

The method of manufacturing the information memory device according tothe present invention is explained next. FIG. 8 shows a process outlineindicating the method of manufacturing an information memory device ofthe present invention. First of all, referring to FIG. 8(a), n-typeimpurity is introduced in the surface of p-type silicon substrate 1 byion implantation or thermal diffusion, thereby n-type source 2 and drain3 are formed. Silicon oxide film 4 is formed thereon by thermaloxidation or high temperature CVD method and then by patterning so thatthe film on the upper part of channel is made thinner. The thermaloxidation temperature is 1000° C. or higher, and the high temperatureCVD method temperature is 900° C. or higher. Further thereon, at lowsubstrate temperature, for example, at room temperature or so, siliconnitride layer 14 is deposited by plasma CVD method.

Next, referring to FIG. 8(b), the surface of silicon nitride layer 14 ispolished by CMP (mechano-chemical polishing method), and flattened sothe silicon oxide film 4 is exposed. Further referring to FIG. 8(c), thefloating gate layer 5 is deposited on the polished surface by CVDmethod. In case of the first embodiment of the present invention, thefloating gate layer 5 has the structure shown in FIG. 7(a). Siliconnitride layer 14 is formed on the floating gate layer 5 by plasma CVDmethod and is patterned so as only the part corresponding to the channelpart left. Further thereon, silicon oxide 4 is deposited by hightemperature CVD method.

Next, referring to FIG. 8(d), silicon oxide film 4 and floating gatelayer 5 are patterned so as only the part corresponding to the channelpart left. Then, the cross-section as shown in FIG. 8(d) is exposed,where only the part surrounding the channel is left (similarly for theother cross-section).

Finally, referring to FIG. 8(e), the patterned substrate is soaked in,for example, HF (hydrofluoric acid) aqueous solution, and only siliconnitride layer 14 is selectively etched, thereby cavity 6 is formed onand under the floating gate layer 5. Then, since silicon nitride layer14 is formed at low temperature by plasma CVD method, it contains manyvacancy, hydrogen bonds, and defect. Therefore, even by wet etching withhydrofluoric acid, the silicon nitride layer is etched faster than thesilicon oxide layers existing on and under the floating gate layer 5.Thereby, substantially only the silicon nitride layer can be selectivelyremoved.

Thereafter, using an annealing oven, the whole substrate is annealed atabout 300° C. Before the annealing, the structure of first and secondsilicon oxide layers 4 constituting insulation film, which is stable atthe forming temperature of the high temperature process, are expandedwith built-in stress from the structure which is stable at the annealingtemperature. Similarly, the structure of silicon oxide layerconstituting the floating gate 5, which is stable at the formingtemperature of the process, is expanded with built-in stress from thestructure which is stable at the annealing temperature, but, since theforming temperature of this process is lower than the formingtemperature of the first and the second silicon oxide layers 4, theextent of expansion is smaller than that of the first and the secondsilicon oxide layers. When annealing the structure comprising the firstand the second silicon oxide layers 4 and the silicon oxide layer whichconstitutes the floating gate 5, the built-in stresses of those layersare released and the structures of those layers shrink to be changed tothe structure stable at the annealing temperature, then, since theextent of expansion of the first and the second silicon oxide layers 4has been larger than that of the silicon oxide layer constituting thefloating gate 5, the first and the second silicon oxide layers shrinkmore greatly. Accordingly it is assumed that, since the floating gatemust become longer than the first and the second silicon oxide layers 4,the floating gate 5 must be deflected inside the cavity 6.

And another assumption may be possible. Since the thermal expansioncoefficient of silicon oxide is positive, the floating gate layerexpands sufficiently as volume relaxation by the thermal treating andthe influence of the space of cavity 6. And, since the floating gatelayer has several 10 nm of thickness against 0.1 to 1 μm of the lengthdirecting toward the channel length, the expansion in the direction offilm thickness is small enough, and the floating gate layer extendseffectively in the direction of channel length. In this case, since thevolume of the gate insulation film 4 holding the floating gate layer 5and the substrate 1 holding the gate insulation film are relativelysufficiently large, the expansion of those are negligible compared tothe expansion of the floating gate layer, and therefore the doublestable states of the floating gate layer which are advantageous inelastic energy may be generated.

The information memory device of the present embodiment thus constitutedis used as a memory cell, and these memory cells, namely, thesetransistors are connected into an array, as illustrated, for example, inFIG. 9, such as that, each of the pluralities of gates of transistorsaligned in the row are connected in common to each word line WD1 to WDn,each of the pluralities of drains of transistors aligned in the columnare connected in common to each data line DL1 to DLm, and all sources oftransistors are connected to the common source line SL, respectively. Inthis way, the memory array according to the present invention is formedby aligning the information memory device of the present invention.

A block diagram of a microcomputer building in the memory cell of thepresent invention is shown in FIG. 10. Inside a microcomputer which isconnected to system-bus through an input buffer and an output buffer, amemory unit is constituted near a central processing unit. By buildingin the memory cell of the present invention to the memory unit, themicrocomputer of high speed and high reliability can be formed.

INDUSTRIAL APPLICABILITY

As is understood from the above-described explanation, the informationmemory device of the present invention has the effect that it can writeinformation not by charging or discharging of electrons to the floatinggate, but by externally applying the voltage to the electrons (or holes)accumulated in the floating gate layer to cause the change of mechanicalstate of the floating gate layer, and has the effect that it can readinformation by the channel current which is changed by the change ofmechanical state of the floating gate layer. In using the mechanicalstate change, since charging or discharging of electrons (or positiveholes) to the floating gate may be done only by once after deviceformation, and reading and writing thereafter may be done only by themechanical operation of the floating gate layer without charging ordischarging of electrons, the problem of device deterioration whichoccurred in conventional flash memories can be solved.

Further, the method of manufacturing the information memory device ofthe present invention in accordance with the present invention has theeffect that it can manufacture the floating gate existing in the spaceof the gate insulation film, which has the elastic double stable state.

Also, the memory array in accordance with the present invention has theeffect that it is a memory having a high operating speed and highreliability, because reading and writing of information can be done bymechanical motion of the floating gate, which can not cause thedeterioration due to the electric current.

1. An information memory device having a semiconductor transistor whichis provided with a semiconductor substrate, a source, a drain, a gate,and a gate insulation film, characterized in that, said gate insulationfilm has a cavity, and in this cavity, there exists a floating gatehaving two stable deflection states, one of which is a stable statedeflecting toward a channel side of said transistor, and the other ofwhich is a stable state deflecting toward said gate side, whereininformation is memorized by said two stable deflection states of saidfloating gate layer.
 2. An information memory device as set forth inclaim 1, characterized in that, said gate insulation film is made ofsilicon oxide.
 3. An information memory device as set forth in claim 1,characterized in that, said floating gate layer is a silicon oxide layercontaining silicon crystal particles.
 4. An information memory device asset forth in claim 1, characterized in that, said floating gate layerhas a structure that a polysilicon thin film layer is sandwiched withtwo silicon oxide layers.
 5. An information memory device as set forthin claim 4, characterized in that, said two silicon oxide layerssandwiching said polysilicon thin film layer have different filmthicknesses each other.
 6. An information memory device as set forth inclaim 1, characterized in that, said floating gate layer has a structurethat a silicon nitride layer is laminated on a silicon oxide layer.
 7. Amethod of manufacturing an information memory device having asemiconductor transistor which is provided with a semiconductorsubstrate, a source, a drain, a gate, and a gate insulation film,wherein said gate insulation film has a cavity, and in this cavity,there exists a floating gate having two stable deflection states, one ofwhich is a stable state deflecting toward a channel side of saidtransistor, and the other of which is a stable state deflecting towardthe gate side, characterized in that, the method of manufacturing saidgate insulation film comprises the steps of: forming a first siliconoxide layer on the semiconductor substrate by high temperature process;forming a caving region for the cavity at the region corresponding to achannel of the transistor by etching said first silicon oxide layer;leaving a silicon nitride layer in said caving region by forming a firstsilicon nitride layer on said surface and etching said silicon nitridelayer; forming a floating gate layer by low temperature process thetemperature of which is lower than the temperature of said hightemperature process; leaving a silicon nitride layer on the regioncorresponding to said cavity region by forming a second silicon nitridelayer on said surface and etching said second silicon nitride layer;forming a second silicon oxide layer on said surface by said hightemperature process and etching a multi layer structure comprising saidsecond silicon oxide layer, said floating gate layer, and said firstsilicon oxide layer into a shape of a gate insulation film; forming saidcavity by removing said first and second silicon nitride layer from saidstructure etched into the shape of gate insulation film; and deflectingsaid floating gate by annealing said structure.
 8. A method ofmanufacturing an information memory device as set forth in claim 7,characterized in that, said step of forming the first silicon oxidelayer by the high temperature process comprises either a thermaloxidation method at 1000° C. or higher, or a high temperature CVD methodat 900° C. or higher.
 9. A method of manufacturing an information memorydevice as set forth in claim 7, characterized in that, said step offorming the first and the second silicon nitride layers by the lowtemperature process comprises a room temperature plasma CVD method. 10.A method of manufacturing an information memory device as set forth inclaim 7, characterized in that, said step of forming the floating gatelayer at the temperature lower than said high temperature processcomprises a CVD method at 700° C. or lower.
 11. A method ofmanufacturing an information memory device as set forth in claim 10,characterized in that, said step of forming the floating gate layer by aCVD method at 700° C. or lower comprises forming a floating gate layerhaving fine silicon crystal particles buried in the oxide film bycontrolling a flow rate of feedstock gas, and a temperature of feedstockgas, and/or a temperature of reactor of the CVD.
 12. A method ofmanufacturing an information memory device as set forth in claim 10,characterized in that, said step of forming the floating gate layer by aCVD method at 700° C. or lower comprises the steps of: forming a firstsilicon oxide layer; forming a layer having fine silicon crystalparticles buried in a oxide film on the surface of said first siliconoxide layer by controlling a flow rate of feedstock gas, and atemperature control of feedstock gas, and/or a temperature of a reactorof the CVD; and forming a second silicon oxide layer on said surface bythe CVD method, wherein the thicknesses of said first silicon oxidelayer and said second silicon oxide layer are made different each other.13. A method of manufacturing an information memory device as set forthin claim 10, characterized in that, said step of forming the floatinggate layer by a CVD method at 700° C. or lower comprises forming asilicon oxide layer by the CVD method and forming a silicon nitridelayer by the CVD method on the surface of said silicon oxide layer. 14.A method of manufacturing an information memory device as set forth inclaim 7, characterized in that, said step of forming the cavity byremoving the first and second silicon nitride layer from the structurecomprises removing the first and the second silicon nitride layer byetching from the exposed side surfaces of the silicon nitride layers ofthe structure with hydrofluoric acid.
 15. A method of manufacturing aninformation memory device as set forth in claim 7, characterized inthat, said step of deflecting the floating gate by annealing thestructure comprises annealing said structure at 300° C. or lower.
 16. Amemory array characterized in that, it uses the information memorydevice as set forth in claim 1 as a memory cell.